1.做一个滴滴打车的出租车a出租车软APP大概多少钱
2.EDA课ç¨è®¾è®¡ï¼ç¨VHDLç¼ç¨ååºç§è½¦è®¡è´¹å¨
3.åºç§è½¦è®¡ä»·å¨
4.网约车牌照申办?
5.EDA 出租车计费器 求大神帮忙 谢谢了 很急啊!!源码!出租车a出租车软
做一个滴滴打车的源码APP大概多少钱
滴滴打车APP价格并不是很贵,十万起步,出租车a出租车软sky测试服源码重点是源码spring源码揭秘豆瓣如何进行推广费用很高,目前比较流行的出租车a出租车软是小程序的开发和推广,性价比和效果都比较好的源码。第1种是出租车a出租车软卖模板为主的网络公司。优点是源码:价格低,几千块钱到万元之间就能搞定,出租车a出租车软方便,源码能够快速上线,出租车a出租车软众人帮平台源码微尘小程序就可以实现。源码缺点是出租车a出租车软:修改功能麻烦,这里需要避免低价陷阱,不要到最后才发现模板性的知识付费源码视频修改功能所花的钱比买模板还贵。而且不是独立的,一个模本卖给很多商家用,模板不是永久使用的,一般每年都要交年费。android源码改图标第2种是主流的方式,定制开发为主的网络公司。优点是:独一无二的,专为你的企业或者店面定制的,功能你来定,要求你来定,后期修改BUG方便,改东西也很方便,最重要的是永久使用权!!缺点是:相对价格比较高!!! 定制版的基本费用在上万元到十几万不等!不过贵也有贵的道理吧,毕竟功能做的更全面一点。最后总结,至于找什么样的小程序开发公司?花多少钱来开发?还是需要看贵公司准备的预算这块。
EDA课ç¨è®¾è®¡ï¼ç¨VHDLç¼ç¨ååºç§è½¦è®¡è´¹å¨
课ç¨è®¾è®¡å 容ä¸è¦æ±
1ï¼ç¨å¼å ³æé®è¡¨ç¤ºèå²ï¼æ¯ä¸ªèå²ä»£è¡¨ç±³ï¼ä¸ªèå²1å ¬éï¼æ¯å ¬é1.4å ï¼è½åæ¥æ¾ç¤ºéç¨åè´¹ç¨ï¼
2ï¼ä½äº2å ¬é5å 计费ï¼é«äº2å ¬éæ»è´¹ç¨=èµ·æ¥è´¹ç¨+ï¼éç¨-2å ¬éï¼*éç¨åä»·+
çåæ¶é´*çååä»·ï¼
3ï¼çåæ¶é´å¤§äº2åéï¼ææ¯åé1.3å 计费ï¼
4ï¼å¯ä»¥è®¾å®èµ·æ¥ä»·åéç¨åä»·ã
ä¸ã设计åçä¸ææ¯æ¹æ³ï¼
å æ¬ï¼çµè·¯å·¥ä½åçåæä¸åçå¾ãå å¨ä»¶éæ©ä¸åæ°è®¡ç®ãçµè·¯è°è¯æ¹æ³ä¸ç»æ说æï¼
软件设计说æ书ä¸æµç¨å¾ã软件æºç¨åºä»£ç ã软件è°è¯æ¹æ³ä¸è¿è¡ç»æ说æã
æ ¹æ®è®¾è®¡è¦æ±ï¼ç³»ç»çè¾å ¥ä¿¡å·clkï¼è®¡ä»·å¼å§ä¿¡å·startï¼çå¾ ä¿¡å·stopï¼éç¨èå²ä¿¡å·finãç³»ç»çè¾åºä¿¡å·æï¼æ»è´¹ç¨æ°C0âc3ï¼è¡é©¶è·ç¦»k0âk1ï¼çå¾ æ¶é´m0âm1çãç³»ç»æ两个èå²è¾å ¥ä¿¡å·clk_k,fin,å ¶ä¸clk_kå°æ ¹æ®è®¾è®¡è¦æ±åé¢æhzï¼hzå1hzåå«ä½ä¸ºå ¬é计费åè¶ æ¶è®¡è´¹çèå²ã两个æ§å¶è¾å ¥å¼å ³startï¼stopï¼æ§å¶è¿ç¨ä¸ºï¼startä½ä¸ºè®¡è´¹å¼å§çå¼å ³ï¼å½start为é«çµå¹³æ¶ï¼ç³»ç»å¼å§æ ¹æ®è¾å ¥çæ åµè®¡è´¹ãå½æä¹å®¢ä¸è½¦å¹¶å¼å§è¡é©¶æ¶ï¼finèå²å°æ¥ï¼è¿è¡è¡é©¶è®¡è´¹ï¼æ¤æ¶çstopéè¦ç½®ä¸º0ï¼å¦éå车çå¾ ï¼å°±æstopå为é«çµå¹³ï¼
并å»é¤finè¾å ¥èå²ï¼è¿è¡çå¾ è®¡è´¹ï¼å½ä¹å®¢ä¸è½¦ä¸ä¸çå¾ æ¶ï¼ç´æ¥å°start置为0ï¼ç³»ç»åæ¢å·¥ä½ï¼ä»·æ ¼å¼å§å½ä¸ºèµ·æ¥ä»·5.0å ã
æ´ä¸ªè®¾è®¡ç±åé¢æ¨¡åï¼è®¡é模åï¼è®¡è´¹æ¨¡åï¼æ§å¶æ¨¡ååæ¾ç¤ºæ¨¡åäºä¸ªé¨åç»æã
å ¶ä¸è®¡é模åæ¯æ´ä¸ªç³»ç»å®ç°éç¨è®¡æ°åæ¶é´è®¡æ°çéè¦é¨åï¼æ§å¶æ¨¡åæ¯å®ç°ä¸å计费æ¹å¼çéæ©é¨åï¼æ ¹æ®æ设计ç使è½ç«¯éæ©æ¯æ ¹æ®éç¨è®¡è´¹è¿æ¯æ ¹æ®çå¾ æ¶é´è®¡è´¹ï¼åæ¶è®¾è®¡éè¿åé¢æ¨¡å产çä¸åé¢ççèå²ä¿¡å·æ¥å®ç°ç³»ç»ç计费ã计é模åéç¨1hzç驱å¨ä¿¡å·ï¼è®¡è´¹æ¨¡åéç¨hzï¼hzç驱å¨ä¿¡å·ï¼è®¡é模åæ¯è®¡æ°ä¸æ¬¡ï¼è®¡é模åå°±å®ç°æ¬¡æè 次计æ°ï¼å³ä¸ºå®ç°è®¡æ¶ç1.3å /minï¼è®¡ç¨æ¶ç1.4å /kmçæ¶è´¹ãç»ææ¡å¾å¦ä¸æ示ï¼
1.ç¾è¿å¶æ¨¡åï¼
å®ç°ç¾ç±³èå²ç驱å¨ä¿¡å·ï¼å 件æ¡å¾å¦å¾3æ示ï¼
å¾3 ç¾è¿å¶æ¨¡åæ¡å¾
æºç¨åºå¦ä¸ï¼
library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all;
entity baijinzhi is
port(start,clk2: in std_logic; --ç§èå²
a: out std_logic_vector(3 downto 0));
end baijinzhi;
architecture rt1 of baijinzhi is
signal count_1:std_logic_vector(3 downto 0);
begin
a<=count_1;
process(start,clk2)
begin
if(start='0')then
count_1<="";
elsif(clk2'event and clk2='1')then
if(count_1="")then
count_1<="";
else
count_1<=count_1+'1';
end if;
end if;
end process;
end rt1
2.计费模å
; å®ç°éç¨åçåæ¶é´ç计费并è¾åºå°æ¾ç¤ºï¼å 件æ¡å¾4å¦ä¸ï¼
å¾4 计费模åæ¡å¾
æºç¨åºå¦ä¸ï¼
Library IEEE;
use IEEE.std_logic_.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity jifei is
port(clk2:in std_logic; --计费驱å¨ä¿¡å·
start:in std_logic; --计费å¼å§ä¿¡å·
c0,c1,c2,c3:buffer std_logic_vector(3 downto 0));
end jifei;
architecture rt1 of jifei is
begin
process(clk2,start)
begin
if start='0'then c3<="";c2<="";c1<="";c0<=""; --èµ·æ¥ä»·5å
elsif clk2'event and clk2='1'then
if c0="" then c0<="";
if c1="" then c1<="";
if c2="" then c2<="";
if c3="" then c3<="";
else c3<=c3+1;
end if;
else c2<=c2+1;
end if;
else c1<=c1+1;
end if;
else c0<=c0+1;
end if;
end if;
end process;
end rt1;
3.å ¬é模å
å®ç°åç¨ç计æ°åè¾åºè®¡è´¹èå²ï¼å 件æ¡å¾5å¦ä¸ï¼
å¾5 å ¬é模åæ¡å¾
æºç¨åºå¦ä¸ï¼
library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all;
entity gongli is
port(clk1,start: in std_logic; --ç¾ç±³èå²
k1,k2,k3,k4: out std_logic_vector(3 downto 0); --éç¨æ¾ç¤º
temp2 : out std_logic);
end gongli;
architecture rt1 of gongli is
signal count_1: std_logic_vector(3 downto 0);
signal count_2: std_logic_vector(3 downto 0);
signal count_3: std_logic_vector(3 downto 0);
signal count_4: std_logic_vector(3 downto 0);
begin
k1<=count_1;
k2<=count_2;
k3<=count_3;
k4<=count_4;
process(start,clk1)
begin
if(start='0')then
count_1<="";
count_2<="";
count_3<="";
count_4<=""; ---å ¬éæ¸ é¶
elsif(clk1'event and clk1='1')then
if(count_1="")then --å ¬é计æ°å¨
count_1<="";count_2<=count_2+1;temp2<='1';
if(count_2="")then
count_2<="";count_3<=count_3+'1';
if(count_3="")then
count_3<="";count_4<=count_4+'1';
end if;
end if;
else
count_1<=count_1+'1';temp2<='0';
end if;
end if;
end process;
end rt1;
4.è¾åºæ¨¡å
å®ç°æææ°æ®çè¾åºï¼å 件æ¡å¾6å¦ä¸ï¼
å¾6 è¾åºæ¨¡åæ¡å¾
æºç¨åºå¦ä¸ï¼
library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all;
entity shuchu is
port(y: in std_logic_vector(3 downto 0);
e: out std_logic_vector(6 downto 0));
end shuchu;
architecture rt1of shuchu is
begin
process
begin
case y is
when""=>e<="";
when""=>e<="";
when""=>e<="";
when""=>e<="";
when""=>e<="";
when""=>e<="";
when""=>e<="";
when""=>e<="";
when""=>e<="";
when""=>e<="";
when others=>e<="";
end case;
end process;
end rt1;
5.æ¾ç¤ºæ¨¡å
å®ç°æææ°æ®çæ¾ç¤ºï¼å 件æ¡å¾7å¦ä¸ï¼
å¾7 æ¾ç¤ºæ¨¡åæ¡å¾
æºç¨åºå¦ä¸ï¼
library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
port(start: in std_logic;
a:in std_logic_vector(3 downto 0); --éæ©ä¿¡å·
c1,c2,c3,c4,out1,out2,out3,out4:in std_logic_vector(3 downto 0); --éç¨æ¾ç¤º,æ¶é´æ¾ç¤ºè¾å ¥
y:out std_logic_vector(3 downto 0)); --éç¨æ¾ç¤º,æ¶é´æ¾ç¤ºè¾åº
end xianshi;
architecture rt1 of xianshi is
begin
process
begin
if(start='0')then
y<="";
else case a is
when ""=> y<=c1 ;
when ""=> y<=c2 ;
when ""=> y<=c3 ;
when ""=> y<=c4 ;
when ""=> y<=out1 ;
when ""=> y<=out2;
when ""=> y<=out3 ;
when ""=> y<=out4;
when others =>y<= "";
end case;
end if;
end process;
end rt1;
6.dian模å
å¾8 dian模åæ¡å¾
æºç¨åºå¦ä¸ï¼
library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all;
entity dian is
port(a: in std_logic_vector(3 downto 0);
e: out std_logic);
end dian;
architecture rt1 of dian is
begin
process
begin
case a is
when ""=>e<='1';
when ""=>e<='1';
when others=>e<='0';
end case;
end process;
end rt1;
ä¸ãä¸å个模å设计åæ
ç³»ç»æ»ä½é¡¶å±æ¡å¾å¦ä¸ï¼
ç³»ç»æ»ä½é¡¶å±æ¡å¾
ç¨åºæç»åè½å®ç°æ³¢å½¢ä»¿ç
1. åé¢æ¨¡å
ç±äºå®éªç®±ä¸æ²¡æhzåhzçæ´æ°åæ¶éä¿¡å·ï¼å æ¤éç¨é¢çè¾å¤§çkhzè¿è¡åé¢ï¼ä»¥è¿ä¼¼å¾å°hzï¼hzå1hzçæ¶éé¢çãéè¿ä»¥ä¸ä¸ç§ä¸åé¢ççèå²ä¿¡å·å®è¡åºç§è½¦è¡é©¶ï¼çå¾ ä¸¤ç§æ åµä¸çä¸å计费ã模åå 件å¦ä¸ï¼
åé¢æ¨¡åæ¡å¾
æºç¨åºå¦ä¸ï¼
Library IEEE;
use IEEE.std_logic_.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity fenpin is
port(clk_k:in std_logic; --ç³»ç»æ¶é
clk_:buffer std_logic; --åé¢
clk_:buffer std_logic; --åé¢
clk_1 : buffer std_logic); --1åé¢
end fenpin ;
architecture rt1 of fenpin is
signal q_:integer range 0 to ; --å®ä¹ä¸é´ä¿¡å·é
signal q_:integer range 0 to ;
signal q_1:integer range 0 to ;
begin
process(clk_k)
begin
If(clk_k' event and clk_k='1')then
If q_= then q_<=0;clk_<=not clk_;
else q_<=q_+1;
end if; --å¾hzé¢çä¿¡å·
If q_= then q_<=0;clk_<=not clk_;
else q_<=q_+1;
end if; --å¾hzé¢çä¿¡å·
If q_1= then q_1<=0;clk_1<=not clk_1;
else q_1<=q_1+1;
end if; --å¾1hzé¢çä¿¡å·
end if;
end process;
end rt1ï¼
2. 计é模å
计é模å主è¦å®æ计æ¶å计ç¨åè½ã
计æ¶é¨åï¼è®¡ç®ä¹å®¢ççå¾ ç´¯ç§¯æ¶é´ï¼å½çå¾ æ¶é´å¤§äº2minæ¶ï¼æ¬æ¨¡åä¸en1使è½ä¿¡å·å为1ï¼å½clk1æ¯æ¥ä¸ä¸ªä¸å沿ï¼è®¡æ¶å¨å°±èªå¢1ï¼è®¡æ¶å¨çéç¨ä¸ºminï¼æ»¡éç¨åèªå¨å½é¶ã
计ç¨é¨åï¼è®¡ç®ä¹å®¢æè¡é©¶çå ¬éæ°ï¼å½è¡é©¶éç¨å¤§äº2kmæ¶ï¼æ¬æ¨¡åä¸en0使è½ä¿¡å·å为1ï¼å½clkæ¯æ¥ä¸ä¸ªä¸å沿ï¼è®¡ç¨å¨å°±èªå¢1ï¼è®¡ç¨å¨çéç¨ä¸ºkmï¼æ»¡éç¨åèªå¨å½é¶ã
å 件æ¡å¾ä¸ºï¼
计é模åæ¡å¾
计é模å仿ç波形为ï¼
æºç¨åºå¦ä¸ï¼
library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jiliang is
port(start:in std_logic; --计费å¼å§ä¿¡å·
fin:in std_logic; --éç¨èå²ä¿¡å·
stop:in std_logic; --è¡é©¶ä¸éçå¾ ä¿¡å·
clk1:in std_logic; --驱å¨èå²
en1,en0:buffer std_logic; --计费å价使è½ä¿¡å·
k1,k0:buffer std_logic_vector(3 downto 0); --è¡é©¶å ¬é计æ°
m1,m0:buffer std_logic_vector(3 downto 0)); --çå¾ æ¶é´è®¡æ°
end jiliang;
architecture rt2 of jiliang is
signal w:integer range 0 to ; --计æ¶èå´0~
begin
process(clk1)
begin
if(clk1'event and clk1='1')then
if start='0' then
w<=0;en1<='0';en0<='0';m1<="";
m0<="";k1<="";k0<="";
elsif stop='1' then --计æ¶å¼å§ä¿¡å·
if w= then
w<=0;
else w<=w+1;
end if;
if m0="" then
m0<="";
if m1="" then
m1<="";
else m1<=m1+1;
end if;
else m0<=m0+1;
end if;
if stop='1' then en0<='0';
if m1&m0>"" then en1<='1'; --è¥çå¾ æ¶é´å¤§äº2minåen1ç½®1
else en1<='0';
end if;
end if;
elsif fin='1' then --éç¨è®¡æ°å¼å§
if k0="" then k0<="";
if k1="" then k1<=""; --计ç¨èå´0~
else k1<=k1+1;
end if;
else k0<=k0+1;
end if;
if stop='0' then
en1<='0';
if k1&k0>"" then
en0<='1'; --è¥è¡ä½¿éç¨å¤§äº2kmï¼åen0ç½®1
else en0<='0';
end if;
end if;
end if;
end if;
end process;
end rt2;
3. æ§å¶æ¨¡å
æ¬æ¨¡å主è¦æ¯éè¿è®¡é模å产çç两个ä¸åçè¾å ¥ä½¿è½ä¿¡å·en0ï¼en1ï¼å¯¹æ¯ä¸ªåé¢æ¨¡åè¾åºçhzï¼hzçèå²è¿è¡éæ©è¾åºçè¿ç¨ï¼æ¬æ¨¡åå®ç°äºåèå²çäºéä¸ï¼æç»ç®ç为äºè®¡è´¹æ¨¡åä¸å¯¹è¡é©¶è¿ç¨ä¸ä¸åçæ¶æ®µè¿è¡è®¡ä»·ã
模åå 件å¦ä¸ï¼
æ§å¶æ¨¡åæ¡å¾
æ§å¶æ¨¡å仿ç波形为ï¼
æºç¨åºå¦ä¸ï¼
Library IEEE;
use IEEE.std_logic_.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity kongzhi is
port(en0,en1:in std_logic; --使è½éæ©ä¿¡å·
clk_in1:in std_logic; --åé¢è¾å ¥ä¿¡å·
clk_in2:in std_logic; --åé¢è¾å ¥ä¿¡å·
clk_out:out std_logic); --è¾åºä¿¡å·
end kongzhi;
architecture rt3 of kongzhi is
begin
process(en0,en1)
begin
if en0='1' then --å®ç°äºéä¸åè½
clk_out<=clk_in1;
elsif en1='1' then
clk_out<=clk_in2;
end if;
end process;
end rt3;
4.计费模å
å½è®¡è´¹ä¿¡å·startä¸ç´å¤äºé«çµå¹³å³è®¡è´¹ç¶ææ¶ï¼æ¬æ¨¡åæ ¹æ®æ§å¶æ¨¡åéæ©åºçä¿¡å·ä»è对ä¸åçåä»·æ¶æ®µè¿è¡è®¡è´¹ãå³è¡ç¨å¨2kmå ï¼èä¸çå¾ ç´¯è®¡æ¶é´å°äº2minå为起æ¥ä»·5å ï¼2kmå¤ä»¥æ¯å ¬é1.4.å 计费ï¼çå¾ ç´¯ç§¯æ¶é´è¶ è¿2minåææ¯åé1.3å 计费ãc0ï¼c1ï¼c2ï¼c3åå«è¡¨ç¤ºè´¹ç¨çæ¾ç¤ºã
模åå 件为ï¼
计费模åæ¡å¾
计费模å仿ç波形为ï¼
æºç¨åºå¦ä¸ï¼
Library IEEE;
use IEEE.std_logic_.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity jifei is
port(clk2:in std_logic; --计费驱å¨ä¿¡å·
start:in std_logic; --计费å¼å§ä¿¡å·
c0,c1,c2,c3:buffer std_logic_vector(3 downto 0));
end jifei;
architecture rt4 of jifei is
begin
process(clk2,start)
begin
if start='0'then c3<="";c2<="";c1<="";c0<=""; --èµ·æ¥ä»·5å
elsif clk2'event and clk2='1'then
if c0="" then c0<="";
if c1="" then c1<="";
if c2="" then c2<="";
if c3="" then c3<=""; --计价èå´0~.9
else c3<=c3+1;
end if;
else c2<=c2+1;
end if;
else c1<=c1+1;
end if;
else c0<=c0+1;
end if;
end if;
end process;
end rt4;
5.æ¾ç¤ºæ¨¡å
æ¾ç¤ºæ¨¡åå®æ计价ï¼è®¡æ¶å计ç¨æ°æ®æ¾ç¤ºã计费æ°æ®éå ¥æ¾ç¤ºæ¨¡åè¿è¡è¯ç ï¼æåéè³ä»¥ç¾å ï¼åå ï¼å ï¼è§ä¸ºåä½å¯¹åºçæ°ç 管ä¸æ¾ç¤ºã计æ¶æ°æ®éå ¥æ¾ç¤ºæ¨¡åè¿è¡è¯ç ï¼æåéè³ä»¥å为åä½å¯¹åºçæ°ç 管ä¸æ¾ç¤ºã计ç¨æ°æ®éå ¥æ¾ç¤ºæ¨¡åè¿è¡è¯ç ï¼æåéè³ä»¥km为åä½çæ°ç 管ä¸æ¾ç¤ºã
模åå 件为ï¼
æ¾ç¤ºæ¨¡åæ¡å¾
æºç¨åºå¦ä¸ï¼
library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all; --å®ä¹åºå
entity xianshi is --å®ä¹å®ä½
port(
clk_scan:in std_logic; --æ«ææ¶éä¿¡å·ç«¯å£è®¾ç½®
c3,c2,c1,c0:in std_logic_vector(3 downto 0); --æ»è´¹ç¨è¾å ¥ç«¯å£
k0,k1:in std_logic_vector(3 downto 0); --éç¨è¾å ¥ç«¯å£
m0,m1:in std_logic_vector(3 downto 0); --çå¾ æ¶é´è¾å ¥ç«¯å£
sel:out std_logic_vector(2 downto 0); --æ§å¶æ°ç 管ä½éä¿¡å·çæ«æä¿¡å·è¾åºç«¯å£
led:out std_logic_vector(6 downto 0); --æ°ç 管çæ§å¶ç«¯å£
led_dp:out std_logic --æ°ç 管çå°æ°ç¹è¾åºç«¯å£
);
end xianshi;
architecture rt5 of xianshi is
signal duan:std_logic_vector(6 downto 0); --æ°ç æ¾ç¤ºç®¡ä¸é´åé
signal shuju:std_logic_vector(3 downto 0); --éæ©è¾å ¥ç«¯çä¸é´åé
signal cnt:std_logic_vector(2 downto 0); --æ§å¶æ°ç 管çä¸é´åé
signal xiaodian:std_logic; --å°æ°ç¹çä¸é´åé
begin
process(clk_scan) --å¼å§è¿ç¨
begin
if clk_scan'event and clk_scan='1' then
cnt<=cnt+1; --æ¯æä¸ä¸ªæ«æä¿¡å·ä¸å沿å®ç°å 1æ«æ
end if;
end process; --ç»æè¿ç¨
process(cnt) --å¼å§è¿ç¨(éæ©æ«ææ¾ç¤ºæ°ç 管)
begin
case cnt is --æ«ææ¶ç»æ¯ä¸ªæ°ç 管èµå¼
when ""=>shuju<=c0;
when ""=>shuju<=c1;
when ""=>shuju<=c2;
when ""=>shuju<=c3;
when ""=>shuju<=k0;
when ""=>shuju<=k1;
when ""=>shuju<=m0;
when ""=>shuju<=m1;
when others=> null;
end case;
if (cnt="" or cnt="")
then xiaodian<='1'; --å¨éç¨åæ»è´¹ç¨ç个ä½å¤æ¾ç¤ºå°æ°ç¹
else xiaodian<='0';
end if;
end process; --ç»æè¿ç¨
process(shuju) --å¼å§è¿ç¨(è¯ç æ¾ç¤º)
begin
case shuju is
when ""=>duan<=""; --0
when ""=>duan<=""; --1
when ""=>duan<=""; --2
when ""=>duan<=""; --3
when ""=>duan<=""; --4
when ""=>duan<=""; --5
when ""=>duan<=""; --6
when ""=>duan<=""; --7
when ""=>duan<=""; --8
when ""=>duan<=""; --9
when others=>null;
end case;
end process;
sel<=cnt;
led<=duan;
led_dp<=xiaodian;
end rt5;
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